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K4B1G0446C Datasheet, PDF (48/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification
◁
K4B1G04(08/16)46C
1Gb DDR3 SDRAM
13.0 Timing Parameters by Speed Grade
[ Table 51 ] Timing Parameters by Speed Bin
Speed
Parameter
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Symbol
tCK(DLL_OFF)
tCK(avg)
Clock Period
tCK(abs)
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tCH(avg)
tCL(avg)
tJIT(per)
tJIT(per, lck)
tJIT(cc)
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac)
levels
Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac)
levels
Data Strobe Timing
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
DQS, DQS output low time
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
DQS, DQS rising edge output access time from rising CK,
CK
DQS, DQS low-impedance time (Referenced from RL-1)
DQS, DQS high-impedance time (Referenced from RL+BL/
2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS faling edge setup time to CK, CK rising edge
DQS,DQS faling edge hold time to CK, CK rising edge
tCH(abs)
tCL(abs)
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tDS(base)
tDH(base)
tRPRE
tRPST
tQSH
tQSL
tWPRE
tWPST
tDQSCK
tLZ(DQS)
tHZ(DQS)
tDQSL
tDQSH
tDQSS
tDSS
tDSH
DDR3-800
MIN
MAX
DDR3-1066
MIN
MAX
DDR3-1333
MIN
MAX
Units
Note
8
-
8
-
8
-
ns
6
See Speed Bins Table
ps
f
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
ps
0.47
0.47
-100
0.53
0.53
100
0.47
0.47
-90
0.53
0.53
90
0.47
0.47
-80
0.53
0.53
80
tCK(avg)
f
tCK(avg)
f
ps
-90
90
-80
80
-70
70
ps
200
180
160
ps
180
160
140
ps
- 147
147
- 132
132
- 118
118
ps
- 175
175
- 157
157
- 140
140
ps
- 194
194
- 175
175
- 155
155
ps
- 209
209
- 188
188
- 168
168
ps
- 222
222
- 200
200
- 177
177
ps
- 232
232
- 209
209
- 186
186
ps
- 241
241
- 217
217
- 193
193
ps
- 249
249
- 224
224
- 200
200
ps
- 257
257
- 231
231
- 205
205
ps
- 263
263
- 237
237
- 210
210
ps
- 269
269
- 242
242
- 215
215
PS
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
0.43
0.43
0.43
0.43
0.43
0.43
tCK(avg)
25
tCK(avg)
26
-
200
-
150
-
125
ps
12,13
0.38
-
0.38
-
0.38
-
tCK(avg)
12,13
-800
400
-600
300
-500
250
ps
13,14, a
-
400
-
300
-
250
ps
13,14, a
75
-
25
-
-10
-
ps
d, 17
150
-
100
-
65
-
ps
d, 17
0.9
0.3
0.38
0.38
0.9
0.3
-400
-800
-
0.4
0.4
-0.25
0.2
0.2
-
NOTE1
-
-
-
-
400
400
400
0.6
0.6
0.25
-
-
0.9
0.3
0.38
0.38
0.9
0.3
-300
-600
-
0.4
0.4
-0.25
0.2
0.2
-
NOTE1
-
-
-
-
300
300
300
0.6
0.6
0.25
-
-
0.9
0.3
0.4
0.4
0.9
0.3
-255
-500
-
0.4
0.4
-0.25
0.2
0.2
-
NOTE1
-
-
-
-
255
250
250
0.6
0.6
0.25
-
-
tCK
tCK
tCK(avg)
tCK(avg)
tCK
tCK
ps
13, 19, b
11, 13, b
13, b
13, b
1
1
12,13
ps
12,13,14
ps
12,13,14
tCK
tCK
tCK(avg)
c
tCK(avg)
c
tCK(avg)
c
Page 48 of 63
Rev. 1.0 June 2007
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