K4B1G0446C Datasheet, PDF (37/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
[ Table 37 ] IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Current
IDD4R
Name
Operating Current Burst Read
Measurement Condition
Timing Diagram Example
Figure 3
CKE
HIGH
External Clock
on
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
CL(IDD)
AL
0
CS
HIGH btw. valid cmds
Command Inputs
(CS, RAS, CAS, WE)
SWITCHING as described in Table 2;
exceptions are Read commands =>
IDD4R Pattern:
R0DDDR1DDDR3DDDR3DDDR4 .....
Rx = Read from bank x;
Definition of D and D: see Table 2
Row, Column Addresses
column addresses
SWITCHING as described in Table 2;
Address Input A10 must be LOW all the
time!
IDD4W
Operating Current Burst Write
HIGH
on
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
CL(IDD)
0
HIGH btw. valid cmds
SWITCHING as described in Table 2;
exceptions are Write commands =>
IDD4W Pattern:
W0DDDW1DDDW2DDDW3DDD W4 ...
Wx = Write to bank x;
Definition of D and D: see Table 2
column addresses
SWITCHING as described in Table 2;
Address Input A10 must be LOW all the
time!
Bank Addresses
bank address cycling (0 ->1 -> 2 -> 3 ...) bank address cycling (0 ->1 -> 2 -> 3 ...)
DQ I/O
Output Buffer DQ,DQS / MR1 bit A12
Rtt_NOM, Rtt_WE
Burst length
Active banks
Idle banks
Precharge Power Down Mode
/ Mode Register Bit
Seamless Read Data Burst (BL8): output Seamless Write Data Burst (BL8): input
data switches every clock, which means data switches every clock, which means
that Read data is stable
that Write data is stable during one clock
during one clock cycle.
cycle.
To achieve Iout = 0mA the output buffer DM is low all the time.
should be switched off by MR1 Bit A12 set
to "1".
off / 1
off / 1
disabled
disabled
8 fixed / MR0 Bits [A1, A0] = {0,0}
8 fixed / MR0 Bits [A1, A0] = {0,0}
all
all
none
none
n.a.
n.a.
IDD7
All Bank Interleave Read Current
HIGH
on
t_CKmin(IDD)
t_RCmin(IDD)
t_RASmin(IDD)
t_RCDmin(IDD)
t_RRDmin(IDD)
CL(IDD)
t_RCDmin-1t_CK
HIGH btw. valid cmds
For patterns see Table 9
STABLE during
DESELECTs
bank address cycling (0 ->1 -> 2 -> 3 ...),
see pattern in Table 9
Read Data (BL8): output data switches
every clock, which means that Read
data is stable during one clock cycle.
To achieve Iout = 0mA the output buffer
should be switched off by MR1 Bit
A12 set to "1".
off / 1
disabled
8 fixed / MR0 Bits [A1, A0] = {0,0}
all
none
n.a.
Page 37 of 63
Rev. 1.0 June 2007