K4B1G0446C Datasheet, PDF (35/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
[ Table 35 ] IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q
Current
IDD2N
Name
Precharge
Standby Current
Measurement Condition
Timing Diagram Example
Figure 2
CKE
HIGH
External Clock
on
t_CK
t_CKmin(IDD)
t_RC
n.a.
t_RAS
n.a.
t_RCD
n.a.
t_RRD
n.a.
CL
n.a.
AL
n.a.
CS
HIGH
Bank Address, Row Addr. and
Command Inputs
SWITCHING as
described in Table 2
Data inputs
SWITCHING
Output Buffer DQ,DQS / MR1 bit A12
off / 1
Rtt_NOM, Rtt_WE
disabled
Burst length
n.a.
Active banks
none
Idle banks
all
Precharge Power
Down Mode / Mode Register Bit ^a
n.a.
IDD2P(1) a
Precharge Power
Down Current
Fast Exit -
MRS A12 Bit = 1
IDD2P(0)
Precharge Power
Down Current
Slow Exit -
MRS A12 Bit = 0
IDD2Q
Precharge Quiet
Standby Current
LOW
on
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
STABLE
LOW
on
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
HIGH
STABLE
STABLE
FLOATING
off / 1
disabled
n.a.
none
all
Fast Exit / 1
(any valid command after
tXP¹)
FLOATING
off / 1
disabled
n.a.
none
all
Slow Exit / 0
Slow exit (RD and ODT
commands must satisfy
tXPDLL-AL)
LOW
on
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
STABLE
STABLE
FLOATING
off / 1
disabled
n.a.
none
all
n.a.
Note :
1. In DDR3 the MRS Bit 12 defines DLL on/off behavior ONLY for precharge power down. There are 2 different Precharge Power Down states possible
: one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0).
2. Because it is an exit after precharge power down the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK
BA[2:0]
ADDR[13:0]
CS
0
0000
7
3FFF
0
0000
RAS
CAS
WE
CMD
D
D
D
D
D
D
D
D
D
D
D
DQ[7:0] _{FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00}
DM
IDD2N /IDD3N Measurement Loop
Figure 21. IDD2N /IDD3N Example (DDR3-800-666, 1Gb X8)
Page 35 of 63
Rev. 1.0 June 2007