K4B1G0446C Datasheet, PDF (17/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
8.2.1 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain
requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(ac) / VIL(ac) ) for ADD/CMD
signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(ac) / VIL(ac) ) for DQ signals)
in every half-cycle preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(ac)/VIL150(ac) is used for
ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK
VDD or VDDQ
VSEH min
VDD/2 or VDDQ/2
VSEL max
VSS or VSSQ
VSEH
CK or DQS
VSEL
time
Figure 3: Single-ended requirement for differential signals.
Note that while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have
a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to
measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing
on timing, but adds a restriction on the common mode charateristics of these signals.
Page 17 of 63
Rev. 1.0 June 2007