K4B1G0446C Datasheet, PDF (33/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
[ Table 34 ] IDD Measurement Conditions for IDD0 and IDD1
Current
IDD0
Name
Operating Current 0
-> One Bank Activate
-> Precharge
Measurement Condition
Timing Diagram Example
CKE
External Clock
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
AL
CS
HIGH
on
t_CKmin(IDD)
t_RCmin(IDD)
t_RASmin(IDD)
n.a.
n.a.
n.a.
n.a.
HIGH between. Activate and Precharge Commands
SWITCHING as described in Table 2;
only exceptions are Activate and Precharge com-
mands; example of IDD0 pattern:
Operating Current 1
-> One Bank Activate
-> Read
-> Precharge
IDD1
Figure 1
HIGH
on
t_CKmin(IDD)
t_RCmin(IDD)
t_RASmin(IDD)
t_RCDmin(IDD)
n.a.
CL(IDD)
0
HIGH between Activate, Read and Precharge
SWITCHING as described in Table 2;
only exceptions are Activate, Read and Precharge
commands; example of IDD1 pattern:
Command Inputs (CS, RAS, CAS, WE)
A0 D D D D D D D D D D D P0
(DDR3-800: tRAS = 37.5ns between (A)ctivate and
(P)recharge to bank 0 ; Definition of D and D: see
Table 2)
A0 D D D D R0 D D D DD D D DD D P0
(DDR3-800 -555: tRCD = 12.5ns between (A)ctivate
and (R)ead to bank 0 ; Definition of D and D: see Table
2)
Row, Column Addresses
Bank Addresses
Data I/O
Output Buffer DQ,DQS / MR1 bit A12
Rtt_NOM, Rtt_WR
Burst length
Active banks
Idle banks
Precharge Power Down Mode /
Mode Register Bit 12
Definition of D and D: See table ##.
Definition of D and D: See table ##.
Row addresses SWITCHING as described in Table 2; Row addresses SWITCHING as described in Table 2;
Address Input A10 must be LOW all the time!
Address Input A10 must be LOW all the time!
bank address is fixed (bank 0)
bank address is fixed (bank 0)
SWITCHING as described in Table 3
Read Data: output data switches every clock, which
means that Read data is stable during one clock cycle.
To achieve Iout = 0mA the output buffer should be
switched off by MR1 Bit A12 set to "1".
When there is no read data burst from DRAM the DQ
I/O should be FLOATING.
off / 1
off / 1
disabled
disabled
n.a.
8 fixed / MR0 Bits [A1, A0] = {0,0}
one ACT-PRE loop
one ACT-RD-PRE loop
all other
all other
n.a.
n.a.
Page 33 of 63
Rev. 1.0 June 2007