K4B1G0446C Datasheet, PDF (41/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
10.2 IDD Specifications
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Conditions
IDD0
Operating one bank active-precharge current;
tCK ₌ tCK(IDD), tRC ₌ tRC(IDD), tRAS ₌ tRASmin(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRC} = ^tRC (IDD), ^tRAS = ^{tRASmin(IDD), tRCD} =
tRCD(IDD); _{CKE is HIGH, CS is HIGH between valid commands;}
Address bus inputs are SWITCHING; Data pattern is same as IDD4W
IDD2P
Precharge power-down current;
All banks idle; tCK = ^tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q
Precharge quiet standby current;
All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2N
Precharge standby current;
All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD3P
Active power-down current;
All banks open; ^tCK = ^tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs
are FLOATING
IDD3N
Active standby current;
All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD),}
tRP ₌ tRP(IDD); _{CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;Data}
bus inputs are SWITCHING
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^tRAS-
max(IDD), ^tRP = ^tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
IDD5B
Burst refresh current;
tCK ₌ tCK(IDD); _{Refresh command at every} tRFC(IDD) _interval;
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD6
Self refresh current;
CK and CK at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6ET
Extended Temperature Range Self-Refresh Current;
CK and CK at 0V; CKE ≤ 0.2V;
Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled, Applicable for
MR2 setting A6=0 and A7=1
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} = ^{tCK(IDD), tRC}
= ^{tRC(IDD), tRRD} = ^{tRRD(IDD), tRCD} = 1*tCK(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;
[ Table 42 ] IDD Specification
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
Page 41 of 63
Rev. 1.0 June 2007