K4B1G0446C Datasheet, PDF (15/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
8.0 AC & DC Input Measurement Levels
8.1 AC and DC Logic input levels for single-ended signals
Symbol
Parameter
V_IH(DC)
V_IL(DC)
V_IH(AC)
V_IL(AC)
VREFDQ(DC)
VREFCA(DC)
dc input logic high
dc input logic low
ac input logic high
ac input logic low
I/O Reference Voltage(DQ)
I/O Reference Voltage(CMD/ADD)
[ Table 7 ] Single Ended AC and DC input levels
DDR3-800/1066/1333
Unit
Min.
Max.
VREF + 100
VDD
mV
VSS
VREF - 100
mV
VREF + 175
-
mV
-
VREF - 175
mV
0.49*VDDQ
0.51*VDDQ
V
0.49*VDDQ
0.51*VDDQ
V
Note :
1. For DQ and DM, V_REF = V_REFDQ . For input only pins except RESET, or V_REF = V_REFCA
2. See 9.6 "Overshoot and Undershoot specifications" on page 23.
3. The ac peak noise on V_REF may not allow V_REF to deviate from V_REF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
Notes
1
1
1,2
1,2
3,4
3,4
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in above
table. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
V_Ref(DC)
V_Ref ac-noise
V_Ref(DC)
VDD
V_Ref(DC)max
VDD/2
V_Ref(DC)min
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef.
"VRef" shall be understood as VRef(DC), as defined in Figure 1.
This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing
and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
Page 15 of 63
Rev. 1.0 June 2007