K4B1G0446C Datasheet, PDF (53/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
Address / Command Setup, Hold and Derating:
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table
53) to the ∆tIS and ∆tIH derating value (see Table 54) respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ’VREF(dc) to ac region’, use nominal slew rate for derating value (see Figure 23). If the actual signal is later than the nominal slew
rate line anywhere between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for
derating value (see Figure 25).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold
(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the
actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(dc) region’, use nominal slew rate for derating value (see Figure
24). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(dc) region’, the slew rate of a tangent line to the
actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 26).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 55).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in Table 54, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 53 ] ADD/CMD Setup and Hold Base-Values for 1V/ns
[ps]
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
reference
tIS(base)
200
125
65
TBD
V_IH/L(ac)
tIH(base)
275
200
140
TBD
V_IH/L(dc)
tIS(base)-AC150
-
-
65+125
TBD+125
V_IH/L(ac)
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
Note : The tIS(base)-AC150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old
of 150mV and another 25ps to acccount for the earlier reference point [(175mv-150mV)/1 V/ns].
[ Table 54 ] Derating values DDR3-800/1066 tIS/tIH-ac/dc based
2.0
1.5
1.0
CMD/
ADD ^0.9
Slew 0.8
rate _0.7
V/ns
0.6
0.5
0.4
4.0 V/ns
∆tIS ∆tIH
88
50
59
34
0
0
-2
-4
-6
-10
-11 -16
-17 -26
-35 -40
-62 -60
∆tIS, ∆tIH Derating [ps] AC/DC based
AC175 Threshold -> VIH(ac) = VREF(dc) + 175mV, VIL(ac) = VREF(dc) - 175mV
CLK,CLK Differential Slew Rate
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH
88
50
88
50
96
58 104 66 112 74
59
34
59
34
67
42
75
50
83
58
0
0
0
0
8
8
16
16
24
24
-2
-4
-2
-4
6
4
14
12
20
20
-6
-10
-6
-10
2
-2
10
6
13
14
-11 -16 -11 -16 -3
-8
5
0
13
8
-17 -26 -17 -26
-9
-18
-1
-10
7
-2
-35 -40 -35 -40 -27 -32 -19 -24 -11 -16
-62 -60 -60 -60 -54 -52 -46 -44 -38 -36
1.2V/ns
∆tIS ∆tIH
120 84
91
68
32
34
30
30
26
24
21
18
15
8
-2
-6
-30 -26
1.0V/ns
∆tIS ∆tIH
128 100
99
74
40
50
38
46
34
40
29
34
23
24
6
10
-22 -10
Page 53 of 63
Rev. 1.0 June 2007