K4B1G0446C Datasheet, PDF (36/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
[ Table36 ] IDD Measurement Conditions for IDD3N and IDD3P(fast exit)
Current
Name
Measurement Condition
Timing Diagram Example
CKE
External Clock
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
AL
CS
Addr. and cmd Inputs
Data inputs
Output Buffer DQ,DQS / MR1 bit A12
Rtt_NOM, Rtt_WE
Burst length
Active banks
Idle banks
Precharge Power
Down Mode / Mode Register Bit ^a
IDD3N
Active Standby Current
Figure 2
HIGH
on
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
HIGH
SWITCHING as described in Table 2
SWITCHING as described in Table 3
off / 1
disabled
n.a.
all
none
n.a.
IDD3P
Active Power-Down Current^a
Always Fast Exit
LOW
on
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
STABLE
STABLE
FLOATING
off / 1
disabled
n.a.
all
none
n.a. (Active Power Down
Mode is always "Fast Exit" with DLL on
Note :
1. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit A12 will be used to switch
between two different precharge power down modes.
Page 36 of 63
Rev. 1.0 June 2007