K4B1G0446C Datasheet, PDF (38/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13
CK
BA[2:0]
000
001
ADDR_a[9:0]
000
3FF
010
001
000
3FF
ADDR_b[10]
ADDR_c[13:11]
000
111
000
111
CS
RAS
CAS
WE
CMD[2:0]
RD
D
D
RD
D
D
D
RD
D
D
D
D
RD
D
DQ[7:0]
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00
DM
Start of Measurement Loop
Figure 22
IDD4R Example (DDR3-800-666,1Gb x8): data DQ is shown but the output buffer should be switched off
(per MR1 Bit A12="1") to achieve Iout = 0mA. Address inputs are split into 3 parts.
[ Table 38 ] IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions
Speed
Bin
Mb/s
Org.
tFAW
[ns]
tFAW
[CLK]
tRRD
[ns]
tRRD
[CLK]
IDD7 Pattern^a
all
800
all
x4/x8
x16
40
16
10
50
20
10
4 ^{A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD A4 RA4 D D A5 RA5 D D A6}
RA6 D D A7 RA7D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5
4
D D A6 RA6 DD A7 RA7 D D D D D D
all
1066
all
x4/x8
37.5
20
7.5
x16
50
27
10
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5
4
D D A6 RA6 DD A7 RA7 D D D D D D
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3 RA3 D D D D D D D A4
6
RA4 D D D D A5RA5 D D D D A6 RA6 D D D D A7 RA7 D D D DD D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5
all
x4/x8
30
20
6
4
D D A6 RA6 DD A7 RA7 D D D D D D
1333
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3RA3 D D D D D D D D D D D D D
all
x16
45
30
7.5
5
A4 RA4 D D DA5 RA5 D D D A6 RA6 D D D A7 RA7 D D D DD D D D D D D D D
all
x4/x8
30
24
6
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3RA3 D D D D D D D A4 RA4 D D
5
D A5 RA5 D DD A6 RA6 D D D A7 RA7 D D D D D D D
1600
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3 RA3 D D D D D D D D D D
all
x16
40
32
7.5
6 D D A4 RA4D D D D A5 RA5 D D D D A6 RA6 D D D D A7RA7 D D D D D D D D
DDDD
Note :
1. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect
Page 38 of 63
Rev. 1.0 June 2007