K4B1G0446C Datasheet, PDF (28/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 14.
1Gb DDR3 SDRAM
VDDQ
CK,CK
DUT_{DQ, DM}
DQS , DQS
TDQS , TDQS
VTT=
RTT ^VSSQ
=25 ohm
VSSQ
Timing Reference Points
BD_REFLOAD_ODT
Figure 14. ODT Timing Reference Load
9.9.2 ODT Timing Definition
Definitions for t_AON, t_AONPD, t_AOF, t_AOFPD and t_ADC are provided in Table28 and subsequent figures. Measurement reference settings
are provided in Table29.
[ Table 28 ] ODT Timing Definitions
Symbol
Begin Point Definition
t_AON
t_AONPD
t_AOF
t_AOFPD
t_ADC
Rising edge of CK - CK defined by the end point of ODTLon
Rising edge of CK - CK with ODT being first registered high
Rising edge of CK - CK defined by the end point of ODTLoff
Rising edge of CK - CK with ODT being first registered low
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4 of ODTLcwn8
End Point Definition
Extrapolated point at VSSQ
Extrapolated point at VSSQ
End point: Extrapolated point at VRTT_Nom
End point: Extrapolated point at VRTT_Nom
End point: Extrapolated point at VRTT_Wr and
VRTT_Nom respectively
Figute
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
[ Table 29 ] Reference Settings for ODT Timing Measurements
Measured
Parameter
RTT_Nom Setting
RTT_Wr Setting
t_AON
t_AONPD
t_AOF
t_AOFPD
t_ADC
R_ZQ/4
R_ZQ/12
R_ZQ/4
R_ZQ/12
R_ZQ/4
R_ZQ/12
R_ZQ/4
R_ZQ/12
R_ZQ/12
NA
NA
NA
NA
NA
NA
NA
NA
R_ZQ/2
V_SW1[V]
0.05
0.10
0.05
0.10
0.05
0.10
0.05
0.10
0.20
V_SW2[V]
0.10
0.20
0.10
0.20
0.10
0.20
0.10
0.20
0.30
Note
Page 28 of 63
Rev. 1.0 June 2007