K4B1G0446C Datasheet, PDF (47/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
[ Table 50 ] DDR3-1333 Speed Bins
Speed
CL-nRCD-nRP
Parameter
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 5
CWL = 5
CWL = 6,7
CWL = 5
CL = 6
CWL = 6
CWL = 7
CWL = 5
CL = 7
CWL = 6
CWL = 7
CWL = 5
CL = 8
CWL = 6
CWL = 7
CL = 9
CWL = 5,6
CWL = 7
CWL = 5,6
CL = 10
CWL = 7
Supported CL Settings
Supported CWL Settings
Symbol
t_AA
t_RCD
t_RP
t_RC
t_RAS
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
1Gb DDR3 SDRAM
DDR3-1333
8-8-8
min
max
12
20
12
-
12
-
48
-
36
9*tREFI
2.5
3.3
Reserved
2.5
3.3
Reserved
Reserved
Reserved
1.875
<2.5
Reserved
Reserved
1.875
<2.5
1.5
<1.875
Reserved
1.5
<1.875
Reserved
1.5
<1.875
(Optional)
5,6,7,8,9
5,6,7
DDR3-1333
9 -9 - 9
min
max
13.5
20
13.5
-
13.5
-
49.5
-
36
9*tREFI
Reserved
Reserved
2.5
3.3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.875
<2.5
Reserved
Reserved
1.5
<1.875
Reserved
1.5
<1.875
(Optional)
6,8,9
5,6,7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n_CK
n_CK
Note
8
1,2,3,4,7
4
1,2,3,7
1,2,3,4,7
4
4
1,2,3,4,7
1,2,3,4,
4
1,2,3,7
1,2,3,4,
4
1,2,3,4
4
1,2,3
5
NOTES:
Absolute Specification (TOPER;VDDQ=VDD=1.5V +/- 0.075V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful-
filed: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen-
cies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ’Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the next valid speed bin limit (i.e.
3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED.
4. ’Reserved’ settings are not allowed. User must program a different value.
5. ’Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and
SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
8. tREFI depends on TOPER
Page 47 of 63
Rev. 1.0 June 2007