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K4B1G0446C Datasheet, PDF (50/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification
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K4B1G04(08/16)46C
1Gb DDR3 SDRAM
[ Table 51 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit
Percharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
Symbol
tXP
tXPDLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WR command to Power Down entry
(BL4MRS)
Timing of WRA command to Power Down entry
(BL4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
ODT high time without write command or with wirte com-
mand and BC4
ODT high time with Write command and BL8
Asynchronous RTT tum-on delay (Power-Down with DLL
frozen)
Asynchronous RTT tum-off delay (Power-Down with DLL
frozen)
ODT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff refer-
ence
RTT dynamic change skew
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is
programmed
DQS/DQS delay after tDQS margining mode is programmed
Setup time for tDQSS latch
Hold time of tDQSS latch
Write leveling output delay
Write leveling output error
tCKE
tCPDED
tPD
tACTPDEN
tPRPDEN
tRDPDEN
tWRPDEN
tWRAPDEN
tWRPDEN
tWRAPDEN
tREFPDEN
tMRSPDEN
ODTH4
ODTH8
tAONPD
tAOFPD
tAON
tAOF
tADC
tWLMRD
tWLDQSEN
tWLS
tWLH
tWLO
tWLOE
DDR3-800
MIN
MAX
max
(3tCK,7.5ns)
max
(10tCK,24ns)
max
(3tCK,7.5ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4 +(tWR/
tCK)
WL + 4 +WR +1
WL + 2 +(tWR/
tCK)
WL +2 +WR +1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
1
9
1
9
-400
400
0.3
0.7
0.3
0.7
40
-
25
-
325
-
325
-
0
9
0
2
DDR3-1066
MIN
MAX
max
(3tCK,7.5ns)
max
(10tCK,24ns)
max
(3tCK,5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4 +(tWR/
tCK)
WL + 4 +WR +1
WL + 2 +(tWR/
tCK)
WL +2 +WR +1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
1
9
1
9
-300
30
0.3
0.7
0.3
0.7
40
-
25
-
245
-
245
-
0
9
0
2
DDR3-1333
MIN
MAX
max
(3tCK,6ns)
max
(10tCK,24ns)
max
(3tCK,5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4 +(tWR/
tCK)
WL + 4 +WR +1
WL + 2 +(tWR/
tCK)
WL +2 +WR +1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
1
9
1
9
-250
250
0.3
0.7
0.3
0.7
40
-
25
-
195
-
195
-
0
9
0
2
Units
Note
2
nCK
tCK
15
nCK
20
nCK
20
nCK
9
nCK
10
nCK
9
nCK
tCK
10
20,21
nCK
nCK
ns
ns
ps
tCK(avg)
tCK(avg)
7,12
8,12
12
tCK
3
tCK
3
ps
ps
ns
ns
Page 50 of 63
Rev. 1.0 June 2007
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