K4B1G0446C Datasheet, PDF (31/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
10.0 Idd Specification Parameters and Test Conditions
10.1 IDD Measurement Conditions
Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows:
[ Table 30 ] Overview of Tables providing IDD Measurement Conditions and DRAM Behavior
Table number
Measurement Conditions
Table 34
IDD0 and IDD1
Table 35
IDD2N, IDD2Q, IDD2P(0), IDD2P(1)
Table 36
IDD3N and IDD3P
Table 37
IDD4R, IDD4W, IDD7
Table 38
IDD7 for different speed grades and different tRRD, tFAW conditions
Table 39
IDD5B
Table 40
IDD6, IDD6ET
Within the tables about IDD measurement conditions, the following definitions are used:
• LOW is defined as V_IN <= V_ILAC(max.); HIGH is defined as V_IN >= V_IHAC(min.);
• STABLE is defined as inputs are stable at a HIGH or LOW level
• FLOATING is defined as inputs are V_REF = V_DDQ / 2
• SWITCHING is defined as described in the following 2 tables.
[ Table 31 ] Definition of SWITCHING for Address and Command Input Signals
SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as:
Address
(Row, Column):
If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks
and change then to the opposite value
(e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax .....
please see each IDDx definition for details
Bank address:
If not otherwise mentioned the bank addresses should be switched like the row/
column addresses - please see each IDDx definition for details
Define D = {CS, RAS, CAS, WE } := {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE } := {HIGH, HIGH,HIGH,HIGH}
Command
(CS, RAS, CAS, WE):
Define Command Background Pattern = D D D D D D D D D D D D ...
If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R) the
Background Pattern Command is substituted by the respective CS, RAS, CAS, WE
levels of the necessary command.
See each IDDx definition for details and figures 1,2,3 as examples.
[ Table 32 ] Definition of SWITCHING for Data (DQ)
SWITCHING for Data (DQ) is defined as
Data
(DQ)
Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means
that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details.
See figures 1,2,3 as examples.
Data Masking (DM)
NO Switching; DM must be driven LOW all the time
Page 31 of 63
Rev. 1.0 June 2007