K4B1G0446C Datasheet, PDF (4/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1.0 Ordering Information
[ Table 1 ] Samsung DDR3 ordering information table
Organization
256Mx4
128Mx8
64Mx16
DDR3-800 (6-6-6)
K4B1G0446C-ZCF7
K4B1G0846C-ZCF7
K4B1G1646C-ZCF7
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. x4/x8/x16 Package - including 16 support balls
DDR3-1066 (7-7-7/8-8-8)
K4B1G0446C-CF8/G8
K4B1G0846C-CF8/G8
K4B1G1646C-CF8/G8
1Gb DDR3 SDRAM
DDR3-1333 (8-8-8/9-9-9)
K4B1G0446C-ZCG9/H9
K4B1G0846C-ZCG9/H9
K4B1G1646C-ZCG9/H9
Package
94 FBGA
94 FBGA
112 FBGA
2.0 Key Features
[ Table 2 ] 1Gb DDR3 C-die Speed bins
Speed
DDR3-800
6-6-6
tCK(min)
2.5
CAS Latency
6
tRCD(min)
15
tRP(min)
15
tRAS(min)
37.5
tRC(min)
52.5
DDR3-1066
7-7-7
8-8-8
1.875
7
8
13.125
15
13.125
15
37.5
37.5
50.625
52.5
DDR3-1333
Unit
8-8-8
9-9-9
1.5
ns
8
9
tCK
12
13.5
ns
12
13.5
ns
36
36
ns
48
49.5
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz f_CK for 800Mb/sec/pin, 533MHz f_CK for 1066Mb/sec/pin,
667MHz f_CK for 1333Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 5, 6, 7, 8, 9, 10, (11 for high density
only)
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T_CASE 85×C, 3.9us at
85×C < T_CASE < 95 ×C
• Asynchronous Reset
• Package : 94 balls FBGA - x4/x8 (with 16 support balls)
112 balls FBGA - x16 (with 16 support balls)
• All of Lead-free products are compliant for RoHS
The 1Gb DDR3 SDRAM C-die is organized as a 32Mbit x 4/16Mbit x 8/
8Mbit x 16 I/Os x 8banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3-
1333) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibra-
tion, On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 1Gb DDR3 device is available in 94ball FBGAs(x4/x8) and 112ball
FBGA(x16)
Note : 1. The functionality described and the timing specifications included
in this data sheet are for the DLL Enabled mode of operation.
2. 1066Mbps CL7 doesn’t have back-ward compatibility with
800Mbps CL5
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device
Operation & Timing Diagram”.
Page 4 of 63
Rev. 1.0 June 2007