MC68HC05B4 Datasheet, PDF (85/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Idle or preceding
transmission _Start
M = 1 (9 data bits)
Idle or next
Stop ^transmission
clock
*
(CPOL = 0, CPHA = 0)
clock
*
(CPOL = 0, CPHA = 1)
clock
*
(CPOL = 1, CPHA = 0)
clock
*
(CPOL = 1, CPHA = 1)
data
012345678
Start LSB
MSB Stop
* LBCL bit controls last data clock
6
Figure 6-10 SCI data clock timing diagram (M=1)
LBCL – Last bit clock
This bit allows the user to select whether the clock associated with the last data bit transmitted
(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if
the LBCL bit is a logic one, and is not output if it is a logic zero.
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by M-bit
(seeTable 6-2).
This bit should not be manipulated while the transmitter is enabled.
Table 6-2 SCI clock on SCLK pin
Data format M-bit LBCL bit
8 bit
0
0
8 bit
0
1
9 bit
1
0
9 bit
1
1
Number of clocks on
SCLK pin
7
8
8
9
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
TPG
MOTOROLA
6-13