MC68HC05B4 Datasheet, PDF(207/298 Page) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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MC68HC05B4 Datasheet, PDF (207/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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E.4.4 RAM parallel bootstrap

The program ï¬rst checks the state of the security bit. If the SEC bit is active, i.e. â0â, the program

will not enter the RAM bootstrap mode and the red LED will ï¬ash. Otherwise the RAM bootstrap

program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before

loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level â0â, or if the

RAM is full, then control is given to the loaded program at address $0050. See Figure E-3 and

Figure E-4.

If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6

according to Figure E-9. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6.

Figure E-10 provides a schematic diagram of a circuit that can be used to load the RAM with short

test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is

accomplished by means of the switches connected to the EPROM higher address lines (A8

through A10). If the user program sets PC0 to level â1â, this will disable the external EPROM, thus

rendering both port A output and port B input available. The EPROM parallel bootstrap loader

schematic can also be used (Figure E-7), provided VPP is at VDD level. The high order address

lines will be at zero. The LEDs will stay off.

tCR

Address

PC5 out

tHO

tADR

tDHR

Data

PC6 in

tHI max

PD4

tEXR max

tADR max (address to data delay; PC6=PC5)

tDHR min (data hold time)

tCR (load cycle time; PC6=PC5)

tHO (PC5 handshake out delay)

tHI max (PC6 handshake in, data hold time)

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5

1 machine cycle = 1/(2f0(Xtal))

16 machine cycles

4 machine cycles

49 machine cycles

5 machine cycles

10 machine cycles

30 machine cycles

Figure E-9 Parallel RAM loader timing diagram

14

MC68HC05B6

Rev. 4

MC68HC705B16

TPG

MOTOROLA

E-19

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