MC68HC05B4 Datasheet, PDF (111/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Table 9-2 Interrupt priorities
Source
Reset
Software interrupt (SWI)
External interrupt (IRQ)
Timer input captures
Timer output compares
Timer overflow
Serial communications
interface (SCI)
Register
—
—
—
TSR
TSR
TSR
SCSR
Flags
—
—
—
ICF1, ICF2
OCF1, OCF2
TOF
TDRE, TC, OR,
RDRF, IDLE
Vector address
$1FFE, $1FFF
$1FFC, $1FFD
$1FFA, $1FFB
$1FF8, $1FF9
$1FF6, $1FF7
$1FF4, $1FF5
$1FF2, $1FF3
Priority
highest
lowest
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
9.2.3 Maskable hardware interrupts
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note: The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
9
9.2.3.1 External interrupt (IRQ)
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit
(INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by
the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and
INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is
recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks
further interrupts until the present one is serviced. The external interrupt service routine address
is specified by the content of memory locations $1FFA and $1FFB.
MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
TPG
MOTOROLA
9-7