MC68HC05B4 Datasheet, PDF (247/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Preliminary H
MC68HC705B32
Maskset errata
This errata section outlines the differences between two previously available masksets
(D59J and D40J) and all other masksets. Unless otherwise stated, the main body of
Appendix G refers to all these other masksets with any differences being noted in this
Preliminary ^{errata section.}
• For the D59J and D40J masksets, the MCU only requires that a logic zero is
applied to the RESET input for 1.5 t_CYC.
• For D59J, 16 cycle POR delay option (t_PORL) is not available
• For the D59J maskset, oscillator divide ratio DIV10 is forced in Bootstrap mode. On
all other revisions DIV2 is forced.
For the D59J:
The STOP Idd is greater than the expected value of 120µA at 5 volts Vdd at a
temperature of 20°C with the CAN module enabled and in SLEEP mode. Typically the
STOP Idd is in the region of 2.0 milliamps at 20°C.
The fault lies with the design of the EPROM array. When the STOP instruction is
executed, the next opcode in memory is present on the data bus. A fault in the EPROM
Preliminary ^{write data latch circuitry causes a latch to be driven to logic 0 on both sides when the}
data bus for that bit is logic 1. This results in increasing STOP Idd of 450µA per data
bus bit set to a logic 1. If all data bus bits are set to logic 1 (i.e. next opcode is $FF, STX
0,X) the STOP Idd shall be in the region of 3.6mA.
The minimum STOP Idd is achieved by ensuring the opcode immediately following the
STOP instruction is data $00. This corresponds to BRSET 0,ADDRESS,LABEL. If the
label points to the next sequential instruction in memory then this has the effect of a 5
cycle NOP but note that the carry bit in the condition code register may be altered by
the BRSET instruction.
14
MC68HC05B6
Rev. 4
MC68HC705B32
TPG
MOTOROLA
H-1