MC68HC05B4 Datasheet, PDF(72/298 Page) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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MC68HC05B4 Datasheet, PDF (72/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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Internal

processor clock

Internal

timer clocks

ï£± T00

ï£´

ï£²

T01

ï£´ T10

ï£³ T11

16-bit

counter

$F456

$F457

$F458

$F459

(Note 1)

5

Output compare

register

CPU writes $F457

(Note 1)

Compare register

latch

$F457

Output compare

ï¬ag and TCMP1,2

(Note 2)

Note:

1 The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state

T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.

1) The output compare ï¬ag is set at the timer state T11 that follows the comparison match ($F457 in this example).

Figure 5-4 Timer state timing diagram for output compare

Internal

processor clock

Internal

timer clocks

ï£± T00

ï£´

ï£²

T01

ï£´ T10

ï£³ T11

16-bit

counter

$FFFF

$0000

$0001

$0002

Timer overï¬ow

ï¬ag

Note:

The timer overï¬ow ï¬ag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared

by a read of the timer status register during the internal processor clock high time, followed by a read of the

counter low register.

Figure 5-5 Timer state timing diagram for timer overï¬ow

MOTOROLA

5-14

PROGRAMMABLE TIMER

TPG

MC68HC05B6

Rev. 4

▷