MC68HC05B4 Datasheet, PDF (270/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

14
Preliminary ^{Table H-8 DC electrical characteristics for 3.3V operation}
(V_DD = 3.3Vdc ± 10%, V_SS = 0Vdc, T_A = –40 to +85°C)
Characteristic⁽¹⁾
Symbol Min
Typ ⁽²⁾
Max
Output voltage
I_LOAD = – 10 µA
I_LOAD = +10 µA
Output high voltage (I_LOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I_LOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
Output low voltage (I_LOAD = 1.6mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
Output low voltage (I_LOAD = 1.6mA)
RESET
V_OH
V_DD – 0.1
—
—
V_OL
—
—
0.1
V_OH V_DD – 0.3 V_DD – 0.1 —
V_OH V_DD – 0.3 V_DD – 0.1 —
V_OL
—
0.1
0.3
V_OL
0.2
0.6
Unit
V
V
V
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V_IH
0.7V_DD
—
V _DD
V
Preliminary ^{Input low voltage}
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ , V_IL
RESET, TCAP1, TCAP2, RDI
Supply current⁽³⁾ (For Guidance Only)
RUN (SM = 0) (See Figure 11-1)
I_DD
RUN (SM = 1) (See Figure 11-2)
I_DD
WAIT (SM = 0) (See Figure 11-3)
I_DD
WAIT (SM = 1) (See Figure 11-4)
I_DD
STOP
0 to 70 (standard)
I_DD
– 40 to 85 (extended)
I_DD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK I_IL
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
I_IN
V_SS
—
0.2V _DD
—
3
TBD
—
1
TBD
—
1.5
TBD
—
0.5
TBD
—
10
TBD
—
10
TBD
—
±0.2
±1
—
±0.2
±1
V
mA
mA
mA
mA
µA
µA
µA
µA
PD0/AN0-PD7/AN7 (channel not selected)
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
I_IN
—
—
±5
µA
PD0/AN0-PD7/AN7 (channel not selected)
Preliminary ^Capacitance
Ports (as input or output), RESET, TDO, SCLK C_OUT
—
IRQ, TCAP1, TCAP2, OSC1, RDI
C_OUT
—
PD0/AN0–PD7/AN7 (A/D off)
C_IN
—
PD0/AN0–PD7/AN7 (A/D on)
C_IN
—
—
12
pF
—
8
pF
12
—
pF
22
—
pF
(1) All I_DD measurements taken with suitable decoupling capacitors across the power supply to suppress the
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT I _DD: measured using an external square-wave clock source (f_OSC = 2.0 MHz); all inputs 0.2 V
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT I _DD: all ports configured as inputs; V_IL = 0.2 V and V_IH = V_DD – 0.2 V: STOP I_DD measured with
OSC1 = V _DD.
WAIT I_DD is affected linearly by the OSC2 capacitance.
MOTOROLA
H-24
MC68HC705B32
TPG
MC68HC05B6
Rev. 4