MC68HC05B4 Datasheet, PDF (223/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Table F-2 EPROM control bits description
E6LAT E6PGM
Description
0
0 Read/execute in EPROM
1
0 Ready to write address/data to EPROM
1
1 programming in progress
ECLK
See Section 4.3.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set) – An erase operation will take place.
0 (clear) – A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
E1LAT — EEPROM programming latch enable bit
1 (set) – Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM.The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t_ERA1 erase time or t_PROG1 programming time, the E1LAT bit has to be reset
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) – Internal charge pump generator switched on.
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table F-3.
Note: The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
MC68HC05B6
Rev. 4
MC68HC705B16N
TPG
MOTOROLA
F-7