MC68HC05B4 Datasheet, PDF(108/298 Page) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HC05B4 Datasheet, PDF (108/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

◁

cannot be disabled by software (writing a âzeroâ to the WDOG bit has no effect at any time). In

addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a â1â to this

bit clears the counter to its initial value and prevents a watchdog timeout.

WDOG â Watchdog enable/disable

The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.

Following a watchdog reset the state of the WDOG bit is as deï¬ned by the mask option speciï¬ed.

1 (set) â Watchdog enabled and counter cleared.

0 (clear) â The watchdog cannot be disabled by software; writing a zero to this

bit has no effect.

The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its ï¬nal

state; seven clocks are necessary to bring the watchdog counter from its clear state to its ï¬nal

state. This reset appears after time tDOG since the last clear or since the enable of the watchdog

counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with

a period less than tDOG.

The reset generated by the watchdog system is apparent at the RESET pin (see Figure 9-2). The

RESET pin level is re-entered in the control logic, and when it has been maintained at level âzeroâ

for a minimum of tDOGL, the RESET pin is released.

9.1.4.1 COP watchdog during STOP mode

The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is

9

executed while the watchdog system is enabled, then a watchdog reset will occur as if there were

a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will

not be affected, thus there will be no tPORL cycles start-up delay. On start-up, the watchdog will be

conï¬gured according to the user speciï¬ed mask option.

9.1.4.2 COP watchdog during WAIT mode

The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to

be one of the options below:

Watchdog enabled â the watchdog counter will continue to operate during WAIT mode and a reset

will occur after time tDOG.

Watchdog disabled â on entering WAIT mode, the watchdog counter system is reset and

disabled. On exiting WAIT mode the counter resumes normal operation.

MOTOROLA

9-4

RESETS AND INTERRUPTS

TPG

MC68HC05B6

Rev. 4

▷