MC68HC05B4 Datasheet, PDF (113/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

9.2.3.2 Miscellaneous register
Miscellaneous
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in Table 9-3.
Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset.
Therefore the device is initialised with negative edge and low level sensitivity.
Table 9-3 IRQ sensitivity
INTP INTN
IRQ sensitivity
0
0 Negative edge and low level sensitive
0
1 Negative edge only
1
0 Positive edge only
1
1 Positive and negative edge sensitive
INTE — External interrupt enable
9
1 (set) – External interrupt function (IRQ) enabled.
0 (clear) – External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 9-3 describes the various triggering options available for the IRQ pin, however it is important
to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible to
change the external interrupt options while the I-bit is set. Any attempt to change the external
interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will
automatically be cleared when selecting a different interrupt option.
Note:
If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
TPG
MOTOROLA
9-9