MC68HC05B4 Datasheet, PDF (59/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

5
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter,
with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The timer can
5
be used for many purposes including measuring pulse length of two input signals and generating
two output signals. Pulse lengths for both input and output signals can vary from several
microseconds to many seconds. In addition, it works in conjunction with the pulse length
modulation (PLM) system, which can also be referred to as the pulse width modulation system, to
execute two 8-bit D/A PLM (pulse length modulation) conversions, with a choice of two repetition
rates. The timer is also capable of generating periodic interrupts or indicating passage of an
arbitrary multiple of four CPU cycles. A block diagram is shown in Figure 5-1, and timing diagrams
are shown in Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5.
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers (except the PLMA and PLMB which use one 8-bit register for each). These registers
contain the high and low byte of that functional segment. Accessing the low byte of a specific timer
function allows full control of that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full
details of which are contained in this section.
Note:
A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
5.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
TPG
MOTOROLA
5-1