MC68HC05B4 Datasheet, PDF (115/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

9.2.4 Hardware controlled interrupt sequence
The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However,
they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2.4.
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the condition code
register is also set, to disable interrupts.
STOP: The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’
until an external interrupt (IRQ) or occurs or the device is reset.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt
(IRQ), a timer interrupt or an SCI interrupt. There are no special WAIT vectors for these
individual interrupts.
9
MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
TPG
MOTOROLA
9-11