MC68HC05B4 Datasheet, PDF (79/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

16X internal sampling clock
RT clock edges for all three examples
1RT 2RT 3RT 4RT 5RT 6RT 7RT 8RT
Idle
Start
RDI
1111 11 111 1 1 0
Start
qualifiers
0
0
0
Start edge
verification samples
Start
RDI
1111 11 111 1 10
Noise
0
1
0
Noise
Start
RDI
1111 10 111 1 10
0
0
0
6
Figure 6-4 SCI examples of start bit sampling technique
Previous bit
Present bit
RDI
16RT 1RT
Samples
8RT 9RT 10RT
Next bit
16RT 1RT
Figure 6-5 SCI sampling technique used on all bits
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 6-4) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 6-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
TPG
MOTOROLA
6-7