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MC68HC05B4 Datasheet, PDF (61/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit | |||
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5.1.1 Counter register and alternate counter register
Timer counter high
Timer counter low
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0018
1111 1111
$0019
1111 1100
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Alternate counter high
$001A
1111 1111
Alternate counter low
$001B
1111 1100
5
The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter
register) or $1A-$1B (alternate counter register). A read from only the less signiï¬cant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read
of the free-running counter or alternate counter register ï¬rst addresses the more signiï¬cant byte
(MSB) ($18 or $1A), the LSB is transferred to a buffer. This buffer value remains ï¬xed after the ï¬rst
MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the
free-running counter or alternate counter register LSB and thus completes a read sequence of the
total counter value. In reading either the free-running counter or alternate counter register, if the
MSB is read, the LSB must also be read to complete the sequence. If the timer overï¬ow ï¬ag (TOF)
is set when the counter register LSB is read then a read of the timer status register (TSR) will clear
the ï¬ag.
The alternate counter register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overï¬ow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a ï¬xed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when
the counter overï¬ows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
In some particular timing control applications it may be desirable to reset the 16-bit free running
counter under software control. When the low byte of the counter ($19 or $1B) is written to, the
counter is conï¬gured to its reset value ($FFFC).
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the ï¬ags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($18 or $1A), then the reset counter operation
terminates the access sequence.
Warning: This operation may affect the function of the watchdog system (see Section 9.1.4). The
PLM results will also be affected while resetting the counter.
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
TPG
MOTOROLA
5-3
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