MC68HC05B4 Datasheet, PDF (56/298 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

a digital read of port D with levels other than V_DD or V_SS on the port D pins will result in greater
power dissipation during the read cycle.
As port D is an input-only port there is no DDR associated with it. Also, at power up or external
reset, the A/D converter is disabled, thus the port is configured as a standard input-only port.
Note: It is recommended that all unused input ports and I/O ports be tied to an appropriate
logic level (i.e. either V_DD or V_SS).
4
4.5
Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.5.1 Port data registers A and B (PORTA and PORTB)
Port A data (PORTA)
Port B data (PORTB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0000
Undefined
$0001
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
The state of the port data registers following reset is not defined.
4.5.2 Port data register C (PORTC)
Port C data (PORTC)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0002
PC2/
ECLK
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM
CTL/ECLK register is set (see Section 4.3).
The state of the port data registers following reset is not defined.
MOTOROLA
4-4
INPUT/OUTPUT PORTS
TPG
MC68HC05B6
Rev. 4