82443GX Datasheet, PDF (99/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Functional Description
NOTE:
1. The 11 column address is used to support 16 KB page size while the 82443GX is programmed in this case to
a page size of 8 KB. As a result, when accesses cross the 8 KB boundary within the page, the 82443GX
closes and re-opens the page as in a page miss case.
2. Proper operation of the 82443GX AGPset with 256-Mbit SDRAM devices has not yet been verified. Intel’s current plans are to
validate this feature in the second half of 1998 when 256-Mbit SDRAM devices are available.
4.3.3 SDRAMC Register Programming
Several timing parameters are programmable when using SDRAM in a Intel^® 440GX AGPset
system. The following table summarizes the programmable parameters.
Table 4-11. Programmable SDRAM Timing Parameters
Parameter
CAS# Latency
RAS# to CAS# Delay
RAS# Precharge
Leadoff CS# assertion
SDRAMC Bit
CL
SRCD
SRP
LCT
Values (DCLKs)
2,3
2,3
2,3
3,4
The 82443GX can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS#
Precharge. Two additional bits are provided for controlling CS# assertion. The first is the Leadoff
Timing bits which effectively control when the command lines (SRAS#, SCAS# and WE#) are
considered valid on the interface and hence when CS# can be asserted for CPU read leadoff cycles.
In the fastest timing mode, CS# can be asserted in clock three. This enables a 7 clock page hit
performance with CAS# Latency two devices and one clock MD to HD delay. This field controls
when the first assertion of CS# occurs for read cycles initiated by the CPU. This assertion may be
for a read, row activate or precharge command. The MA lines along with the command lines
(SRAS#, SCAS# and WE#) are driven in clock two, however the clock to output delay timing is
slower than the other modes. Use of this mode may require a lightly loaded SDRAM interface.
4.3.4
SDRAM Paging Policy
Open page arbitration is a paging policy which leaves pages open when handing off ownership of
DRAM among masters, and places no restrictions on the number of rows which may have open
pages at any given time.
Features include:
• Pipelined arbitration allows row/bank/page operations for next cycle to occur while current
DRAM access is performed.
• Maintaining 2, or 4 banks open at once per row, in up to 8 rows at a time.
4.4
PCI Interface
The 82443GX Host Bridge provides a PCI bus interface that is compliant with the PCI Local Bus
Specification, Revision 2.1. The implementation is optimized for high-performance data streaming
when the 82443GX is acting as either the target or the initiator on the PCI bus. The 82443GX
supports the conventional PCI interface referred to as PCI and AGP/PCI interface referred to as
AGP for PCI transactions and AGP for PCI transactions using the AGP enhanced protocols. AGP
cycles using the enhanced protocols are non-snoopable cycles targeted at DRAM.
82443GX Host Bridge Datasheet
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