82443GX Datasheet, PDF (19/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-4. Primary PCI Interface Signals (Sheet 2 of 2)
Name
Type
Description
C/BE[3:0]#
PAR
PLOCK#
TRDY#
SERR#
STOP#
Command/Byte Enable: PCI Bus Command and Byte Enable signals are
multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]#
define the bus command. During the data phase C/BE[3:0]# are used as byte
enables. The byte enables determine which byte lanes carry meaningful data. PCI
Bus command encoding and types are listed below.
C/BE[3:0]# Command Type
0000
0001
0010
I/O
0011
0100
PCI
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Reserved (Dual Address Cycle)
Memory Read Line
Memory Write and Invalidate
Parity: PAR is driven by the 82443GX when it acts as a PCI initiator during address
I/O _{and data phases for a write cycle, and during the address phase for a read cycle. PAR}
PCI ^{is driven by the 82443GX when it acts as a PCI target during each data phase of a}
PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.
Lock: PLOCK# indicates an exclusive bus operation and may require multiple
I/O _{transactions to complete. When PLOCK# is asserted, non-exclusive transactions may}
PCI ^{proceed. The 82443GX supports lock for CPU initiated cycles only. PCI initiated}
locked cycles are not supported.
I/O ^{Target Ready: TRDY# is an input when the 82443GX acts as a PCI initiator and an}
output when the 82443GX acts as a PCI target. The assertion of TRDY# indicates the
PCI _{target agent's ability to complete the current data phase of the transaction.}
System Error: The 82443GX asserts this signal to indicate an error condition. The
SERR# assertion by the 82443GX is enabled globally via SERRE bit of the PCICMD
register. SERR# is asserted under the following conditions:
In an ECC configuration, the 82443GX asserts SERR#, for single bit (correctable)
ECC errors or multiple bit (non-correctable) ECC errors if SERR# signaling is enabled
via the ERRCMD control register. Any ECC errors received during initialization should
be ignored.
• The 82443GX asserts SERR# for one clock when it detects a target abort during
82443GX initiated PCI cycle.
• The 82443GX can also assert SERR# when a PCI parity error occurs during the
I/O
address or data phase.
PCI • The 82443GX can assert SERR# when it detects a PCI address or data parity
error on AGP.
• The 82443GX can assert SERR# upon detection of access to an invalid entry in
the Graphics Aperture Translation Table.
• The 82443GX can assert SERR# upon detecting an invalid AGP master access
outside of AGP aperture and outside of main DRAM range (i.e. in the 640k - 1M
range or above TOM).
• The 82443GX can assert SERR# upon detecting an invalid AGP master access
outside of AGP aperture.
• The 82443GX asserts SERR# for one clock when it detects a target abort during
82443GX initiated AGP cycle.
I/O ^{Stop: STOP# is an input when the 82443GX acts as a PCI initiator and an output}
when the 82443GX acts as a PCI target. STOP# is used for disconnect, retry, and
PCI _{abort sequences on the PCI Bus.}
NOTE:
1. All PCI interface signals conform to the PCI Rev 2.1 specification.
82443GX Host Bridge Datasheet
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