82443GX Datasheet, PDF (67/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.38
Default Value:
Access:
Size:
0000-0000-0000-0000h
Read/Write
64 bits
This register provides 8 bytes general purpose read/write registers for the BIOS to perform the
configuration routine. The 82443GX will provide this 8 byte register in the PCI configuration space
of the 82443GX device0 on bus 0. The registers in this range will be defined as read/write and will
be initialized to all 0’s after PCIRST#. The BIOS will can access these registers through the normal
PCI configuration register mechanism, accessing 1,2 or 4 bytes in every data access.
Bit
64:0 BIOS Work Space.
Description
DWTC—DRAM Write Thermal Throttling Control Register
(Device 0)
Offset:
Default:
Access:
Size:
E0h–E7h
0000_0000_0000_0000h
Read/Write/Lock
64 bits
A locking mechanism is included to protect contents of this register as well as the DRAM Read
Thermal Throttling Control register described below.
Bits
63
62:46
45:38
37:26
25:20
19:13
12:3
2:0
Description
Throttle Lock (TLOCK). This bit secures the DRAM thermal throttling control registers.
1 = All configuration register bits in E0h–E7h & E8h–EFh (read throttle control) are read-only.
0 = Default
Reserved
Global DRAM Write Sampling Window (GDWSW). This 8-bit value is multiplied by 4 to define
the length of time in milliseconds (0–1020) over which the number of QWords written is counted.
Global QWord Threshold (GQT). The 12-bit value held in this field is multiplied by 215 to arrive
at the number of QWords that must be written within the Global DRAM Write Sampling Window in
order to cause the thermal throttling mechanism to be invoked.
Throttle Time (TT). This value provides a multiplier between 0 and 63 which specifies how long
thermal throttling remains in effect as a number of Global DRAM Write Sampling Windows. For
example, if GDWSW is programmed to 1000_0000b and TT is set to 01_0000b, then thermal
throttling will be performed for ~2 seconds once invoked (128 ms * 16).
Throttle Monitoring Window (TMW). The value in this register is padded with four 0’s to specify
a window of 0–2047 DRAM CLKs with 16 clock granularity. While the thermal throttling
mechanism is invoked, DRAM writes are monitored during this window—if the number of QWords
written during the window reaches the Throttle QWord Maximum, then write requests are blocked
for the remainder of the window.
Throttle QWord Maximum (TQM). The Throttle QWord Maximum defines the maximum number
of QWords between 0–1023 which are permitted to be written to DRAM within one Throttle
Monitoring Window while the thermal throttling mechanism is in effect.
DRAM Write Throttle Mode. Normal DRAM write monitoring and thermal throttling operation are
enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved.
000-011 = Intel Reserved
100 = Normal Operations
101-111 = Intel Reserved
82443GX Host Bridge Datasheet
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