82443GX Datasheet, PDF (16/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-1. Host Interface Signals (Sheet 2 of 2)
Name
Type
Description
ADS#
BNR#
BPRI#
BREQ0#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
I/O
GTL+
I/O
GTL+
O
GTL+
O
GTL+
I/O
GTL+
O
GTL+
I/O
GTL+
I/O
GTL+
I/O
GTL+
I
GTL+
I/O
GTL+
I/O
GTL+
I/O
GTL+
Address Strobe: The CPU bus owner asserts ADS# to indicate the first of two
cycles of a request phase.
Block Next Request: Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the CPU bus pipeline depth.
Priority Agent Bus Request: The 82443GX is the only Priority Agent on the CPU
bus. It asserts this signal to obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was asserted.
Symmetric Agent Bus Request: Asserted by the 82443GX when CPURST# is
asserted to configure the symmetric bus agents. BREQ0# is negated 2 host clocks
after CPURST# is negated.
Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
Defer: The 82443GX generates a deferred response as defined by the rules of the
82443GX’s dynamic defer policy. The 82443GX also uses the DEFER# signal to
indicate a CPU retry response.
Data Ready: Asserted for each cycle that data is transferred.
Hit: Indicates that a caching agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.
Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line. Also
driven in conjunction with HIT# to extend the snoop window.
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#,
until the negation of HLOCK# must be atomic, i.e. no PCI or AGP snoopable access
to DRAM is allowed when HLOCK# is asserted by the CPU.
Request Command: Asserted during both clocks of request phase. In the first clock,
the signals define the transaction type to a level of detail that is sufficient to begin a
snoop request. In the second clock, the signals carry additional information to define
the complete transaction type. The transactions supported by the 82443GX Host
Bridge are defined in the Host Interface section of this document.
Host Target Ready: Indicates that the target of the CPU transaction is able to enter
the data transfer phase.
Response Signals: Indicates type of response according to the following the table:
RS[2:0] Response type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by 82443GX)
100
Hard Failure (not driven by 82443GX)
101
No data response
110
Implicit Writeback
111
Normal data response
NOTE:
1. All of the signals in the host interface are described in the CPU External Bus Specification. The preceding
table highlights 82443GX specific uses of these signals.
2-2
82443GX Host Bridge Datasheet