82443GX Datasheet, PDF (23/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-7. Clocks, Reset, and Miscellaneous (Sheet 2 of 2)
Name
GCLKO
CRESET#
TESTIN#
Type
O
CMOS
O
CMOS
I
CMOS
Description
AGP Clock Out: The frequency is 66 MHz. The GCLKOUT output is used to feed
both the reference input pin on the 82443GX and the AGP compliant device.
Delayed CPU Reset: CRESET# is a delayed copy of CPURST#. This signal is used
to control the multiplexer for the CPU strap signals. CRESET# is delayed from
CPURST# by two host clocks.
Note: This pin requires an external pull-up resistor. If not used, no pull up is required.
Test Input: This pin is used for manufacturing, and board level test purposes.
Note: This pin has an internal 50K ohm pull-up.
Table 2-8. Power Management Interface
Name
Type
Description
CLKRUN#
SUSTAT#
I/OD
CMOS
I
CMOS
Primary PCI Clock Run: The 82443GX requests the central resource (PIIX4E) to
start or maintain the PCI clock by the assertion of CLKRUN#. The 82443GX tristates
CLKRUN# upon deassertion of PCIRST# (since CLK is running upon deassertion of
reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop,
Mobile requires (8.2k–10K) pull-up. Otherwise, a 100 Ohm pull down is required.
Suspend Status (from PIIX): SUSTAT# signals the system suspend state transition
from the PIIX4E. It is used to isolate the suspend voltage well and enter/exit DRAM
self-refresh mode. During POS/STR SUSTAT# is active.
GXPWROK
I
CMOS
GX Power OK: GXPWROK input must be connected to the PWROK signal that
indicates valid power is applied to the 82443GX.
Table 2-9. Reference Pins
Name
Description
GTLREF[B:A] GTL Buffer voltage reference input
VTT[B:A]
GTL Threshold voltage for early clamps
VCC
Power pin @ 3.3V
VSS
Ground
REF5V
PCI 5V reference voltage (for 5V tolerant buffers)
AGPREF
External Input Reference
2.7
Power-Up/Reset Strap Options
Table 2-10 is the list of all power-up options that are loaded into the 82443GX during cold reset.
The 82443GX is required to float all the signals connected to straps during cold reset and keep
them floated for a minimum of 4 host clocks after the end of cold reset sequence. Cold reset
sequence is performed when the 82443GX power is applied.
Note: All signals used to select power-up strap options are connected to either internal pull-down or pull-
up resistors of minimum 50K ohms (maximum is 150K). That selects a default mode on the signal
during reset. To enable different modes, external pull ups or pull downs (the opposite of the internal
82443GX Host Bridge Datasheet
2-9