82443GX Datasheet, PDF (20/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
2.4
Primary PCI Sideband Interface
Table 2-5. Primary PCI Sideband Interface Signals
Name
PHOLD#
PHLDA#
WSC#
PREQ[4:0]#
PGNT[4:0]#
Type
I
PCI
O
PCI
O
CMOS
I
PCI
O
PCI
Description
PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus
ownership. The 82443GX will flush and disable the CPU-to-PCI write buffers before
granting the PIIX4E the PCI bus via PHLDA#. This prevents bus deadlock between
PCI and ISA.
PCI Hold Acknowledge: This signal is driven by the 82443GX to grant PCI bus
ownership to the PIIX4E after CPU-PCI post buffers have been flushed and disabled.
Write Snoop Complete. This signal is asserted active to indicate that all that the
snoop activity on the CPU bus on the behalf of the last PCI-DRAM write transaction is
complete and that is safe to send the APIC interrupt message.
PCI Bus Request: PREQ[4:0]# are the PCI bus request signals used as inputs by the
internal PCI arbiter.
PCI Grant: PGNT[4:0]# are the PCI bus grant output signals generated by the internal
PCI arbiter.
2.5
AGP Interface Signals
There are 17 new signals added to the normal PCI group of signals that together constitute the AGP
interface. The sections below describe their operation and use, and are organized in five groups:
• AGP Addressing Signals
• AGP Flow Control Signals
• AGP Status Signals
• AGP Clocking Signals - Strobes
• PCI Signals
Table 2-6. AGP Interface Signals (Sheet 1 of 3)
Name
PIPE#
SBA[7:0]
RBF#
Type
I
AGP
I
AGP
I
AGP
Description
AGP Sideband Addressing Signals¹
Pipelined Read: This signal is asserted by the current master to indicate a full width
address is to be queued by the target. The master queues one request each rising
clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are
queued across the AD bus. PIPE# is a sustained tri-state signal from masters
(graphics controller) and is an input to the 82443GX. Note that initial AGP designs
may not use PIPE#.
Sideband Address: This bus provides an additional bus to pass address and
command to the 82443GX from the AGP master. Note that, when sideband
addressing is disabled, these signals are isolated (no external/internal pull-ups are
required).
AGP Flow Control Signals
Read Buffer Full. This signal indicates if the master is ready to accept previously
requested low priority read data. When RBF# is asserted the 82443GX is not allowed
to return low priority read data to the AGP master on the first block. RBF# is only
sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is not required to
implement this signal.
2-6
82443GX Host Bridge Datasheet