82443GX Datasheet, PDF (44/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.16 PAM[6:0]—Programmable Attribute Map Registers
(Device 0)
Address Offset:
Default Value:
Attribute:
59h (PAM0) – 5Fh (PAM6)
00h
Read/Write
The 82443GX allows programmable memory attributes on 13 Legacy memory segments of various
sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers
are used to support these features. Cacheability of these areas is controlled via the MTRR registers
in the Pentium Pro processor. Two bits are used to specify memory attributes for each memory
segment. These bits apply to both host accesses and PCI initiator accesses to the PAM areas. These
attributes are:
RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment
are claimed by the 82443GX and directed to main memory. Conversely, when RE = 0, the
host read accesses are directed to PCI.
WE Write Enable. When WE = 1, the host write accesses to the corresponding memory
segment are claimed by the 82443GX and directed to main memory. Conversely, when
WE = 0, the host write accesses are directed to PCI.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding and are defined in Table 3-2.
Table 3-2. Attribute Bit Assignment
Bits [7, 3]
Reserved
x
x
x
x
Bits [6, 2]
Reserved
x
x
x
x
Bits [5, 1]
WE
0
0
1
1
Bits [4, 0]
RE
Description
Disabled. DRAM is disabled and all accesses are
0
directed to PCI. The 82443GX does not respond as a
PCI target for any read or write access to this area.
Read Only. Reads are forwarded to DRAM and writes
are forwarded to PCI for termination. This write protects
1
the corresponding memory segment. The 82443GX will
respond as a PCI target for read accesses but not for
any write accesses.
Write Only. Writes are forwarded to DRAM and reads
0
are forwarded to the PCI for termination. The 82443GX
will respond as a PCI target for write accesses but not
for any read accesses.
Read/Write. This is the normal operating mode of main
memory. Both read and write cycles from the host are
1
claimed by the 82443GX and forwarded to DRAM. The
82443GX will respond as a PCI target for both read and
write accesses.
As an example, consider a BIOS that is implemented on the expansion bus. During the
initialization process, the BIOS can be shadowed in main memory to increase the system
performance. When BIOS is shadowed in main memory, it should be copied to the same address
location. To shadow the BIOS, the attributes for that address range should be set to write only. The
BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus.
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82443GX Host Bridge Datasheet