82443GX Datasheet, PDF (21/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-6. AGP Interface Signals (Sheet 2 of 3)
Name
Type
Description
ST[2:0]
ADSTB_A
ADSTB_B
SBSTB
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
O
AGP
I/O
AGP
I/O
AGP
I
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I
AGP
AGP Status Signals
Status Bus: This bus provides information from the arbiter to a AGP Master on what
it may do. ST[2:0] only have meaning to the master when its GGNT# is asserted.
When GGNT# is deasserted these signals have no meaning and must be ignored.
000 Indicates that previously requested low priority read data is being returned to
the master.
001 Indicates that previously requested high priority read data is being returned to
the master.
010 Indicates that the master is to provide low priority write data for a previously
queued write command.
011 Indicates that the master is to provide high priority write data for a previously
queued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the master has been given permission to start a bus transaction.
The master may queue AGP requests by asserting PIPE# or start a PCI
transaction by asserting FRAME#. ST[2:0] are always an output from the
82443GX and an input to the master.
AGP Clocking Signals - Strobes
AD Bus Strobe A: This signal provides timing for double clocked data on the AD bus.
The agent that is providing data drives this signal. This signal requires an 8.2K ohm
external pull-up resistor.
AD Bus Strobe B: This signal is an additional copy of the AD_STBA signal. This
signal requires an 8.2K ohm external pull-up resistor.
Sideband Strobe: THis signal provides timing for a side-band bus. This signal
requires an 8.2K ohm external pull-up resistor.
AGP FRAME# Protocol SIgnals (similar to PCI)²
Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains deasserted
by its own pull up resistor.
Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP compliant
master is ready to provide all write data for the current transaction. Once IRDY# is
asserted for a write operation, the master is not allowed to insert wait states. The
assertion of IRDY# for reads indicates that the master is ready to transfer to a
subsequent block (32 bytes) of read data. The master is never allowed to insert wait
states during the initial data transfer (32 bytes) of a read transaction. However, it may
insert wait states after each 32 byte block is transferred.
(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)
Graphics Target Ready: New meaning. GTRDY# indicates the AGP compliant
target is ready to provide read data for the entire transaction (when the transfer size is
less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block
(32 bytes) of data when the transfer size is greater than 32 bytes. The target is
allowed to insert wait states after each block (32 bytes) is transferred on both read
and write transactions.
Graphics Stop: Same as PCI. Not used by AGP.
Graphics Device Select: Same as PCI. Not used by AGP.
Graphics Request: Same as PCI. (Used to request access to the bus to initiate a
PCI or AGP request.)
82443GX Host Bridge Datasheet
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