82443GX Datasheet, PDF (94/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Functional Description
4.3
4.3.1
DRAM Interface
The 82443GX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64-bit
memory data plus 8 ECC) DRAM array. The DRAM type supported is Synchronous (SDRAM).
The 82443GX does not support mixing of SDRAM and Registered SDRAM. The 82443GX
DRAM interface runs at 100 MHz. The DRAM controller interface is fully configurable through a
set of control registers. Complete descriptions of these registers are given in the Register Section. A
brief overview of the registers which configure the DRAM interface is provided in this section.
The fifteen multiplexed address lines, MA[14:0], allow the 82443GX to support 2M, 4M, 8M,
16M, 32M, and 64M x72/64 DIMMs. Asymmetric addressing is supported. The 82443GX has
sixteen CS# lines, used in pairs enabling the support of up to eight 64/72-bit rows of DRAM. For
write operations of less than a QWord in size, the 82443GX will either perform a byte-wise write
(non-ECC protected configuration) or a read-modify-write cycle by merging the write data on a
byte basis with the previously read data (ECC or EC configurations). The 82443GX targets
SDRAM with CL2 and CL3 and supports both single and double-sided DIMMs. The 82443GX
provides refresh functionality with programmable rate (normal DRAM rate is 1 refresh/15.6ms).
The 82443GX can be configured via the Paging Policy Register to keep multiple pages open within
the memory array. Pages can be kept open in all rows of memory. When 4 bank SDRAM devices
are used for a particular row, up to 4 pages can be kept open within that row.
The DRAM interface of the 82443GX is configured by the DRAM Control Register, DRAM
Timing Register, SDRAM Control Register, bits in the NBXCFG and the eight DRAM Row
Boundary (DRB) Registers. The DRAM configuration registers noted above control the DRAM
interface to select SDRAM or registered SDRAM, RAS timings, and CAS rates. The eight DRB
Registers define the size of each row in the memory array, enabling the 82443GX to assert the
proper CSA/B# pair for accesses to the array.
DRAM Organization and Configuration
The 82443GX supports 64/72-bit DRAM configurations. In the following discussion the term row
refers to a set of memory devices that are simultaneously selected by a CSA/B# pair. A row may be
composed of discrete DRAM devices, single-sided or double-sided DIMMs.
The 82443GX has multiple copies of many of the signals interfacing to memory. The interface
consists of the following pins.
• Multiple copies
— MAA[14:0], MAB[12:11,9:0]# and MAB[14,13,10]
— CSA[7:0]#, CSB[7:0]#
— SRASA#, SRASB#
— SCASA#, SCASB#
— WEA#, WEB#
— DQMA[7:0], DQMB[5,1]
• Single Copy
— MD[63:0]
— MECC[7:0]
— GCKE
— FENA (FET switch control for 4 DIMM configurations designed with FETs)
Two CS# lines are provided per row. These are functionally equivalent. The extra copy is provided
for loading reasons. The two SRAS#’s, SCAS#’s and WE#’s are also functionally equivalent and
each copy drives two rows of DRAM. Most pins utilize programmable strength output buffers
4-14
82443GX Host Bridge Datasheet