82443GX Datasheet, PDF (122/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Testability
Figure 6-1. Waveform of Test Mode
Test mode activation without cold reset (toggling of GXPWROK)
DCLKWR
GXPWROK
PCIRST#
TESTIN#
PREQ[4:0]#
NAND Chain A
Test Mode
NAND Chain A
test_tm1.vsd
6.2
Tester Powerup Sequence
Figure 6-2 shows the typical powerup sequence of 443GX on a tester. At time 0, PCIRST# and
TESTIN# must be asserted. The GXPWROK signal must also be asserted to indicate that a cold
reset is in progress. Once PCIRST# is deasserted TESTIN# can also be safely deasserted on the
fourth DCLKWR positive edge. PCIRST# and TESTIN# should not deassert at the same time
because a race condition prevents the circuit from guaranteeing proper latching of primary test
modes.
Figure 6-2. Typical power-up sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DCLKWR
GXPWROK
min of 4 DCLKWR periods
PCIRST#
min of 8 DCLKWR periods
TESTIN#
min of 4 DCLKWR periods
PREQ[2:0]#
PREQ[4:3]#
Normal Operation
Output Enable
SUSTAT#
Test Mode
suspend mode disabled as long as SUSTAT# remains deasserted
Async Tristate
Output Enable
test_tm2.vsd
6-2
82443GX Host Bridge Datasheet