82443GX Datasheet, PDF (62/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.32
AGPCMD—AGP Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
A8–ABh
00000000h
Read/Write
32 bits
This register provides control of the AGP operational parameters.
Bit
31:10
9
8
7:2
1:0
Description
Reserved.
AGP Side Band Enable. This bit enables the side band addressing mechanism.
1 = Enable.
0 = Disable.
AGP Enable. When disabled, the 82443GX ignores all AGP operations, including the sync
cycle. Any AGP operations received while this bit is set to 1 is serviced even if this bit is reset
to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command
being delivered in 1X mode the command will be issued. When this bit is set to 1 the
82443GX will respond to AGP operations delivered via PIPE#, or to operations delivered via
SBA if the AGP Side Band Enable bit is also set to 1.
The AGP parameters in the AGPCMD and AGPCTRL registers must be set prior to setting
this bit ‘1’. With the exception of the GTLB_ENABLE (bit 7, AGPCTRL), and ATTBASE
register (offset B8h), which can be modified dynamically.
1 = Enable.
0 = Disable.
Reserved.
AGP Data Transfer Rate. One (and only one) bit in this field must be set to indicate the
desired data transfer rate (Bit 0 for 1X, Bit 1 for 2X). The same bit must be set on both master
and target. Configuration software will update this field by setting only one bit that
corresponds to the capability of AGP master (after that capability has been verified by
accessing the same functional register within the AGP masters configuration space.)
00 = default
01 = 1x data transfer rate.
10 = 2x data transfer rate.
11 = Illegal
NOTE: This field applies to AD and SBA buses.
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82443GX Host Bridge Datasheet