82443GX Datasheet, PDF (46/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.17 DRB[0:7]—DRAM Row Boundary Registers (Device 0)
Address Offset:
Default Value:
Access:
Size:
60h (DRB0) – 67h (DRB7)
01h
Read/Write
8 bits/register
The 82443GX supports 8 physical rows of DRAM. The width of a row is 64 bits. The DRAM Row
Boundary Registers define upper and lower addresses for each DRAM row. Contents of these 8-bit
registers represent the boundary addresses in 8 MB granularity. For example, a value of 01h
indicates 8 MB.
60h DRB0 = Total memory in row0 (in 8 MB)
61h DRB1 = Total memory in row0 + row1 (in 8 MB)
62h DRB2 = Total memory in row0 + row1 + row2 (in 8 MB)
63h DRB3 = Total memory in row0 + row1 + row2 + row3 (in 8 MB)
64h DRB4 = Total memory in row0 + row1 + row2 + row3 + row4 (in 8 MB)
65h DRB5 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 (in 8 MB)
66h DRB6 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 (in 8 MB)
67h DRB7 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 + row7
(in 8 MB)
The DRAM array can be configured with single or double-sided DIMMs using parts listed in
Table 4-9. The array also supports x4 width DRAM components on registered DIMMs. Each
register defines an address range that will cause a particular CS# line to be asserted (e.g., if the first
DRAM row is minus 8 MB, then accesses within the 0 to 8 MByte range will cause CSx0#/
RASx0# to be asserted). The DRAM Row Boundary (DRB) Registers are programmed with an 8-
bit upper address limit value. This upper address limit is compared to bits [30:23] of the requested
address, for each row, to determine if DRAM is being targeted.
To specify a memory size of 2 GB, the DRB7 must be set to 00h. When this value is set, the
82443GX internally detects this value and sets the internal “2 GB system memory size” signal. It is
cleared otherwise.
Note:
DRBx and 2GB Decoding. The ability to detect a total system memory of 2 GB is possible for
DRB7 only. It is possible, however, to achieve 2 GB of memory in lower DRAM rows when some
or all the populated rows are 512 MB each. If the total memory size at DRBx, where x<7, is 2 GB,
then BIOS must set DBRx to 0FFh and the total memory available is 2 GB minus 8 MB. For the
following rows (from x+1 to 7), the DRB is set to 0FFh.
Note: DRAM is selected only if address[31:30] are zero.
Bit
Description
Row Boundary Address. This 8-bit value is compared against address lines A[30:23] to
7:0
determine the upper address limit of a particular row (i.e., DRB minus previous DRB = row size).
NOTE: When PCIRST# assertion occurs during POS/STR, these bits are not reset to 01h.
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82443GX Host Bridge Datasheet