82443GX Datasheet, PDF (65/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.36
MBFS—Memory Buffer Frequency Select Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
CA–CCh
000000h
Read/Write
24 bits
The settings in this register enable the 100 MHz buffers for each of the following signal groups.
Bit
Description
23
Reserved
MAA[14:0], WEA#, SRASA#, SCASA#. This bit enables 100 MHz buffers for MAA[14:0], WEA#,
SRASA#, SCASA#.
22
0 = Reserved
1 = 100 MHz
MAB[12:11, 9:0]# & MAB[14,13,10], WEB#, SRASB#, SCASB#. This bit enables 100 MHz
buffers for MAB[12:11, 9:0]# & MAB[14,13,10], WEB#, SRASB#, SCASB#. Note that the
21
address’s MABx# are inverted copies of MAA, with the exception of MAB[14,13,10].
0 = Reserved
1 = 100 MHz
MD [63:0] [Control 2]). This bit enables 100 MHz buffers for MD [63:0] [Control 2]. (Refer to the
corresponding MBSC register for programming details).
20
0 = Reserved
1 = 100 MHz
MD [63:0] [Control 1]. This bit enables 100 MHz buffers for MD [63:0] [Control 1]. (Refer to the
corresponding MBSC register for programming details).
19
0 = 100 MHz A
1 = 100 MHz B
MECC [7:0] [Control 2]. This bit enables 100 MHz buffers for MECC [7:0] [Control 2]. (Refer to
the corresponding MBSC register for programming details).
18
0 = 100 MHz A
1 = 100 MHz B
MECC [7:0] [Control 1). This bit enables 100 MHz buffers for MECC [7:0] [Control 1]. (Refer to
the corresponding MBSC register for programming details).
17
0 = Reserved
1 = 100 MHz
CSB7#. This bit enables 100 MHz buffers for CSB7#.
16
0 = Reserved
1 = 100 MHz
CSA7#. This bit enables 100 MHz buffers for CSA7#.
15
0 = Reserved
1 = 100 MHz
CSB6#. This bit enables 100 MHz buffers for CSB6#.
14
0 = Reserved
1 = 100 MHz
CSA6#. This bit enables 100 MHz buffers for CSA6#.
13
0 = Reserved
1 = 100 MHz
82443GX Host Bridge Datasheet
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