82443GX Datasheet, PDF (93/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Functional Description
Table 4-7. Host Special Cycles with 82443GX
BE[7:0}#
Special
Cycle Type
Action Taken
0000
0101
0000
0110
0000
0111
all others
Flush
Acknowledge
Stop Clock
Acknowledge
SMI
Acknowledge
Reserved
This transaction is issued when an agent has completed a cache sync and flush
operation in response to an earlier FLUSH# signal assertion. The 82443GX
claims this cycle and retires it.
This transaction is issued when an agent enters Stop Clock mode. This cycle is
claimed by the 82443GX and propagated to the PCI as a Special Stop Grant
Cycle. This cycle is completed on the CPU bus after it is terminated on the PCI
via a master abort mechanism.
This transaction is first issued when an agent enters the System Management
Mode (SMM).
NOTE:
1. None of the host bus special cycles is propagated to the AGP interface.
4.2.2
Symmetric Multiprocessor (SMP) Protocol Support
The Intel^® 440GX AGPset is optimized for uniprocessor system and also supports the symmetrical
multiprocessor configurations of up to two CPUs on the host bus.
When configured for dual-processor, the Intel^® 440GX AGPset-based platform must integrate an
I/O APIC functionality and WSC# signaling mechanism must be enabled.
4.2.3
In-Order Queue Pipelining
The 82443GX interface to the CPU bus includes a four deep in-order queue to track pipelined bus
transactions.
4.2.4
Frame Buffer Memory Support (USWC)
To allow for high speed write capability for graphics, the Pentium Pro processor family has
introduced USWC memory type. The USWC (uncacheable, speculative, write-combining) memory
type provides a write-combining buffering mechanism for write operations. A high percentage of
graphics transactions are writes to the memory-mapped graphics region, normally known as the
linear frame buffer. Reads and writes to USWC are non-cached and can have no side effects.
In the case of graphics, current 32-bit drivers (without modifications) would use Partial Write
protocol to update the frame buffer. The highest performance write transaction on the CPU bus is
the Line Write.
82443GX Host Bridge Datasheet
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