82443GX Datasheet, PDF (55/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.23
SDRAMC—SDRAM Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
76h–77h
00h
Read/Write
16 bits
Bit
15:8
7:5
4
3
2
1
0
Description
Reserved
SDRAM Mode Select (SMS). These bits allow the 82443GX to drive various commands to the
SDRAMs. These special modes are intended for initialization at power up.
SMS Mode
000 Normal SDRAM Operation. (default)
001 NOP Command Enable. In this mode all CPU cycles to SDRAM result in NOP
Command on the SDRAM interface.
010 All Banks Precharge Enable. In this mode all CPU cycles to SDRAM result in an All
Banks Precharge Command on the SDRAM interface.
011 Mode Register Set Enable. In this mode all CPU cycles to SDRAM result in a mode
register set command on the SDRAM interface. The command is driven on the
MAx[14:0] lines. MAx[2:0] must always be driven to 010 for burst of 4 mode. MA3 must
be driven to 1 for interleave wrap type. MAx4 needs to be driven to the value
programmed in the CAS# Latency bit. MAx[6:5] should always be driven to 01.
MAx[12:7] must be driven to 000000. BIOS must calculate and drive the correct host
address for each row of memory such that the correct command is driven on the
MAx[12:0] lines.
100 CBR Enable. In this mode all CPU cycles to SDRAM result in a CBR cycle on the
SDRAM interface.
101 Reserved.
110 Reserved.
111 Reserved.
Note: BIOS must take into consideration MAB inversion when programming DIMM slots 2 and 3.
SDRAMPWR.
0 = Reserved
1 = SDRAMPWR should be set to ‘1’.
Note: When PCIRST# assertion occurs during POS/STR, these bits are not reset to 0.
Leadoff Command Timing (LCT). These bits control when the SDRAM command pins
(SRASx#, SCASx# and WEx#) and CSx# are considered valid on leadoffs for CPU cycles.
0 = 4 CS# Clock
1 = 3 CS# Clock
Note: For all platforms, BIOS should leave the LCT bit set to its default value of 0.
CAS# Latency (CL). This bit controls the number of CLKs between when a read command is
sampled by the SDRAMs and when the 82443GX samples read data from the SDRAMs. If a
given row is populated with a registered SDRAM DIMM, an extra clock is inserted between the
read command the when the 82443GX samples read data. For a registered DIMM with CL=2,
this bit should be set to 1.
0 = 3 DCLK CAS# latency.
1 = 2 DCLK CAS# latency.
SDRAM RAS# to CAS# Delay (SRCD). This bit controls the number of DCLKs from a Row
Activate command to a read or write command.
0 = 3 clocks will be inserted between a row activate command and either a read or write
command.
1 = 2 clocks will be inserted between a row activate and either a read or write command.
SDRAM RAS# Precharge (SRP). This bit controls the number of DCLKs for RAS# precharge.
0 = 3 clocks of RAS# precharge.
1 = 2 clocks of RAS# precharge.
82443GX Host Bridge Datasheet
3-31