82443GX Datasheet, PDF (123/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Testability
6.3
Test Mode Details
6.3.1 Nand CHAIN A
The NAND chain A test mode is used for board level connectivity test. Its main purpose is to
detect connectivity shorts between adjacent pins and to check proper bonding between I/O pads
and I/O pins. Figure 6-3 is a conceptual diagram of the NAND chain.
To help reduce the board level test cost, the NAND chain is limited to 60 pins per chain. This is
accomplished by implementing 9 separate NAND chains.
Figure 6-3. NAND Chain A0 Connectivity
Inputs
NAND Chain A0
82443GX
Vcc
Outputs
HA21#
HA6#
HA4#
AD21
SBA[7]
SBA[6]
SBA[5]
SBA[4]
SBA[3]
SBA[2]
SBA[1]
SBA[0]
test_cha.vsd
Figure 6-4 shows an example NAND tree test. At first, all the input pins are driven to logic 1. Next,
each input pin is driven to logic 0, in a sequence, so that the output pin, in this case SBA[0],
toggles. By observing the NAND chain output pin, one can detect shorted and unconnected pins.
82443GX Host Bridge Datasheet
6-3