82443GX Datasheet, PDF (35/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.3
PCICMD—PCI Command Register (Device 0)
Address Offset:
Default:
Access:
Size
04–05h
0006h
Read/Write
16 bits
This 16-bit register provides basic control over the 82443GX PCI interface ability to respond to
PCI cycles. The PCICMD Register enables and disables the SERR# signal, 82443GX response to
PCI special cycles, and enables and disables PCI bus master accesses to main memory.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Descriptions
Reserved.
Fast Back-to-Back. Fast back-to-back cycles to different PCI targets are not implemented by the
82443GX.
0 = Hardwired to 0.
SERR# Enable (SERRE). Note that this bit only controls SERR# for the PCI bus. Device #1 has
its own SERRE bit to control error reporting for the bus conditions occurred on the AGP bus. Two
control bits are used in a logical OR manner to control SERR# pin driver.
1 = If this bit is set to a 1, the 82443GX’s SERR# signal driver is enabled and SERR# is asserted
when an error condition occurs, and the corresponding bit is enabled in the ERRCMD
register. The error status is reported in the ERRSTS and PCISTS registers. Also, if this bit is
set and the 82443GX’s PCI parity error reporting is enabled by the PERRE bit located in this
register, then the 82443GX will report address and data parity errors (when it is potential
target).
0 = SERR# is never driven by the 82443GX.
Address/Data Stepping. Not implemented (hardwired to 0).
Parity Error Enable (PERRE). Note that the PERR# signal is not implemented by the 82443GX.
1 = Enable. Address and data parity errors are reported via SERR# mechanism (if enabled via
SERRE bit).
0 = Disable. Address and data parity errors are not reported via the 82443GX SERR# signal.
(NOTE: Other types of error conditions can be still signaled via SERR# mechanism.)
NOTE: The 82443GX PCI bus interface is still required to generate parity even if parity error
reporting is disabled via this bit.
Reserved.
Memory Write and Invalidate Enable. The 82443GX never uses this command.
0 = Hardwired to 0.
Special Cycle Enable. The 82443GX ignores all special cycles generated on the PCI.
0 = Hardwired to 0.
Bus Master Enable (BME). The 82443GX does not support disabling of its bus master
capability on the PCI Bus.
1 = Hardwired to 1, permitting the 82443GX to function as a PCI Bus master.
Memory Access Enable (MAE). This bit enables/disables PCI master access to main memory
(DRAM). The 82443GX always allows PCI master access to main memory.
1 = Hardwired to 1.
I/O Access Enable (IOAE). The 82443GX does not respond to PCI bus I/O cycles.
0 = Hardwired to 0.
82443GX Host Bridge Datasheet
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