82443GX Datasheet, PDF (17/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-2 lists the CPU bus interface signals which are NOT supported by the Intel^® 440GX
AGPset.
Table 2-2. Host Signals Not supported by the 82443GX
Signal
A[35:32]#
AERR#
AP[1:0]#
BINIT#
DEP[7:0]#
IERR#
INIT#
BERR#
RP#
RSP#
BP[3:2]#
BPM[1:0]#
Function
Address
Address Parity Error
Address Parity
Bus Initialization
Data Bus ECC/Parity
Internal Error
Soft Reset
Bus Error
Request Parity
Response Parity
Signal
BreakPoint
BreakPoint Monitor
Not Supported By 82443GX
Extended addressing (over 4 GB)
Parity protection on address bus
Parity protection on address bus
Checking for bus protocol violation and protocol recovery mechanism
Enhanced data bus integrity
Direct internal error observation via IERR# pin
Implemented by PIIX4E, BIST supported by external logic.
Unrecoverable error without a bus protocol violation
Parity protection on ADS# and PREQ[4:0]#
Parity protection on RS[2:0]#
Breakpoint status
Breakpoint and performance monitor
2.2
DRAM Interface
Table 2-3. DRAM Interface Signals (Sheet 1 of 2)
Name
CSA[7:0]#
/CSB[7:0]#
DQMA[7:0]
DQMB[1,5]
GCKE
SRAS[B,A]#
FENA
SCAS[B,A]#
Type
O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
Description
Chip Select (SDRAM): These pins perform the function of selecting the
particular SDRAM components during the active state.
Note that there are 2 copies of CS# per physical memory row to improve the
loading.
Input/Output Data Mask A-side: These pins control A half of the memory array
and act as synchronized output enables during read cycles and as a byte enables
during write cycles.
Input/Output Data Mask B-side (SDRAM): The same function as the
corresponding signals for the A side (DQMAx). These signals are used to reduce
the loading in an ECC configuration.
Global CKE: Global CKE is used in a 4 DIMM configuration requiring power
down mode for the SDRAM. External logic must be used to implement this
function.
SDRAM Row Address Strobe: The SRAS[B,A]# signals are multiple copies of
the same logical SRASx signal (for loading purposes) used to generate SDRAM
command encoded on SRASx/SCASx/WE signals.
FET Enable (FENA): FENA is used to select the proper MD path through the
FET switches in a 4 DIMM configuration.
SDRAM Column Address Strobe: The SCAS[B,A]# signals are multiple copies
of the same logical SCASx signal (for loading purposes) used to generate
SDRAM command encoded on SRASx/SCASx/WE signals.
82443GX Host Bridge Datasheet
2-3