82443GX Datasheet, PDF (96/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Functional Description
4.3.1.1 Configuration Mechanism For DIMMS
Detection of the type of DRAM installed on the DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL, SDA
and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the 82443GX for detecting the size and type of memory
installed. Type and size detection must be done via the serial presence detection pins.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the 82443GX DRAM registers must
be initialized. The 82443GX must be configured for operation with the installed memory types.
Detection of memory type and size is done via the System Management Bus (SMB) interface on
the PIIX4E. This two wire bus is used to extract the DRAM type and size information from the
serial presence detect port on the DRAM DIMMs.
DRAM DIMMs contain a 5 pin serial presence detect interface, including SCL (serial clock), SDA
(serial data) and SA[2:0]. Devices on the SMBus bus have a seven bit address. For the DRAM
DIMMs, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0]
pins. SCL and SDA are connected directly to the System Management Bus on the PIIX4E. Thus
data is read from the Serial Presence Detect port on the DIMMs via a series of IO cycles to the
south bridge. BIOS essentially needs to determine the size and type of memory used for each of the
eight rows of memory in order to properly configure the 82443GX memory interface.
DRAM Register Programming
The Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength,
Row Type (on a row by row basis), SDRAM Timings, Row Sizes and Row Page Sizes. Table 4-8
lists a subset of the data available through the on board Serial Presence Detect ROM on each
DIMM.
Table 4-8. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
2
3
4
5
11
12
17
36-41
42
Function
Memory Type (SDRAM)
# of Row Addresses, not counting Bank Addresses
# of Column Addresses
# of banks of DRAM (Single or Double sided) DIMM
ECC, no ECC
Refresh Rate
# Banks on each SDRAM Device
Access Time from Clock for CAS# Latency 1 through 7
Data Width of SDRAM Components
Table 4-8 is only a subset of the defined SPD bytes on the DIMMs. For example, to program the
DRB (DRAM Row Boundary) registers, the size of each row must be determined. The number of
row addresses (byte 3) plus the number of column addresses (byte 4) plus the number of banks on
each SDRAM device (byte 17) collectively determines the total address depth of a particular row of
SDRAM. Since a row is always 64 data bits wide, the size of the row is easily determined for
programming the DRB registers.
The 82443GX uses the DRAM Row Type information in conjunction with the DRAM timings set
in the DRAM Timing Register to configure DRAM accesses optimally.
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82443GX Host Bridge Datasheet