82443GX Datasheet, PDF (27/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.1.2
Bit
31
30:24
23:16
15:11
10:8
7:2
1:0
Descriptions
Configuration Enable (CFGE). When this bit is set to 1 accesses to PCI configuration space are
enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled.
Reserved.
Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle
is either the 82443GX or the PCI Bus that is directly connected to the 82443GX, depending on the
Device Number field. A type 0 Configuration Cycle is generated on PCI if the Bus Number is
programmed to 00h and the 82443GX is not the target. If the Bus Number is non-zero a type 1
configuration cycle is generated on PCI or AGP with the Bus Number mapped to AD[23:16] during
the address phase.
Device Number. This field selects one agent on the PCI bus selected by the Bus Number. During
a Type 1 Configuration cycle this field is mapped to AD[15:11]. During a Type 0 Configuration
Cycle this field is decoded and one bit among AD[31:11] is driven to a 1. The 82443GX is always
Device Number 0 for the Host-to-PCI bridge entity and Device Number 1 for the Host- AGP entity.
Therefore, the 82443GX internally references the AD11 and AD12 pins as corresponding IDSELs
for the respective devices during PCI configuration cycles. NOTE: The AD11 and AD12 must not
be connected to any other PCI bus device as IDSEL signals.
Function Number. This field is mapped to AD[10:8] during PCIx configuration cycles. This allows
the configuration registers of a particular function in a multi-function device to be accessed. The
82443GX only responds to configuration cycles with a function number of 000b; all other function
number values attempting access to the 82443GX (Device Number = 0 and 1, Bus Number = 0)
will generate a master abort.
Register Number. This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2]
during PCI configuration cycles.
Reserved.
CONFDATA—Configuration Data Register
I/O Address:
Default Value:
Access:
Size:
0CFCh
00000000h
Read/Write
32 bits
CONFDATA is a 32 bit read/write window into configuration space. The portion of configuration
space that is referenced by CONFDATA is determined by the contents of CONFADD.
Bit
31:0
Descriptions
Configuration Data Window (CDW). If bit 31 of CONFADD is 1 any I/O reference that falls in the
CONFDATA I/O space will be mapped to configuration space using the contents of CONFADD.
82443GX Host Bridge Datasheet
3-3