82443GX Datasheet, PDF (57/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.3.25
PMCR—Power Management Control Register (Device 0)
Address Offset:
Default Value:
Access
Size
7Ah
0000_S0S0b
Read/Write
8 Bits
Bit
Description
7
Intel Reserved
ACPI Control Register Enable (SCRE).
6
1 = Enable. The ACPI control register in the 82443GX is enabled, and all CPU cycles to IO
address 0022h are handled by the 82443GX and are not forwarded to PCI.
0 = Disable (default). All CPU cycles to IO address 0022h are passed on to the PCI bus.
5
Intel Reserved
Normal Refresh Enable (NREF_EN). This bit is used to enable normal refresh operation
following a POS/STR state. After coming out of reset the software must set this bit before
4
doing an access to memory.
1 = Enable
0 = Disable
3
Intel Reserved
Gated Clock Enable (GCLKEN). GCLKEN enables internal dynamic clock gating in the
82443GX when a AGPset “IDLE” state occurs. This happens when the 82443GX detects an
2
idle state on all its buses.
1 = Enable
0 = Disable
AGP Disable (AGP_DIS). This register bit is Read Only and a configuration write to it is
ignored.
1
1 = Disable. The AGP interface and the clocks of AGP associated logic are permanently
disabled. This mode is entered using a strapping option that is sampled by the 82443GX
during reset.
0 = Enable
CPU reset without PCIRST enable (CRst_En). This bit enables the 82443GX to assert CPU
reset without an incoming PCIRST#. This option allows the reset of the processor when the
system is coming out of POS state. Defaults to ‘0’ upon PCIRST# assertion.
0
1 = Enable
0 = Disable
NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.
82443GX Host Bridge Datasheet
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